makefile: pattern rules for subdirectory


Here is my project:<br />

project |--- main.cpp |--- makefile |--- test |--- Test.cpp |--- Test.h

Here is the makefile:<br />

g++1x:=g++ -std=c++14 -stdlib=libc++ -MMD -MP cflags:= -Wall -lncurses PATHS:=./ ./test/ TARGET:=matrix.out SRC:=$(foreach PATH,$(PATHS),$(wildcard $(PATH)/*.cpp)) OBJDIR:=.obj OBJ:=$(addprefix $(OBJDIR)/,$(notdir $(SRC:.cpp=.o))) .PHONY: install install: $(OBJDIR) $(TARGET) $(OBJDIR): mkdir -p $(OBJDIR) $(TARGET): $(OBJ) $(g++1x) $(cflags) -o $@ $^ -g $(OBJDIR)/%.o: %.cpp $(g++1x) -c -o $@ $< -g $(OBJDIR)/%.o: ./test/%.cpp $(g++1x) -c -o $@ $< -g -include $(addprefix $(OBJDIR)/,$(notdir $(SRC:.cpp=.d))) .PHONY: clean clean: rm -f $(TARGET) rm -rf $(OBJDIR)

It works well but I have two questions:<br /> 1) Is it possible to avoid foreach for PATHS so that I can use the same makefile for all of cpp projects?<br /> 2) As you see, to generate main.o and Test.o I write two blocks:<br />$(OBJDIR)/%.o: ./test/%.cpp and $(OBJDIR)/%.o: %.cpp.<br /> Is it possible to write only once?<br /> I've tried as below but it doesn't work:<br />

$(OBJDIR)/%.o: $(foreach PATH,$(PATHS),$(wildcard $(PATH)/%.cpp)) $(g++1x) -c -o $@ $< -g

I've even tried like this but it doesn't work still:<br />

$(OBJDIR)/%.o: %.cpp ./test/%.cpp $(g++1x) -c -o $@ $< -g


You should keep the source tree into your object tree. This way it will be easier to create <em>global</em> rules and keep dependencies.

# Use the shell find command to get the source tree SOURCES := $(shell find * -type f -name "*.c") OBJDIR := .objects # Keep the source tree into the objects tree OBJECTS := $(addprefix $(OBJDIR)/,$(SOURCES:.c=.o)) all: mytarget mytarget: $(OBJECTS) $(CC) $^ -o $@ # As we keep the source tree we have to create the # needed directories for every object $(OBJECTS): $(OBJDIR)/%.o: %.c mkdir -p $(@D) $(CC) -MMD -MP -c $< -o $@ -include $(OBJECTS:.o=.d) <hr /><pre class="lang-sh prettyprint-override">$ make mkdir -p .objects cc -MMD -MP -c main.c -o .objects/main.o mkdir -p .objects/test cc -MMD -MP -c test/test.c -o .objects/test/test.o cc .objects/main.o .objects/test/test.o -o mytarget $ tree -a . ├── main.c ├── Makefile ├── mytarget ├── .objects │   ├── main.d │   ├── main.o │   └── test │   ├── test.d │   └── test.o └── test ├── test.c └── test.h 3 directories, 9 files <hr />

<strong>EDIT</strong>: You can reduce the number of mkdir to the minimum by adding the object directory as an <a href="https://www.gnu.org/software/make/manual/make.html#Prerequisite-Types" rel="nofollow">order only prerequisites</a>:

# Do not create the directory $(OBJECTS): $(OBJDIR)/%.o: %.c $(CC) -MMD -MP -c $< -o $@ # Every target finishing with "/" is a directory $(OBJDIR)%/: mkdir -p $@ # Add the "directory/" as an order only prerequisite $(foreach OBJECT,$(OBJECTS),$(eval $(OBJECT): | $(dir $(OBJECT))))


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