VHDL directly comparing vectors


I was wondering if its possible to directly compare 2 vectors with eachother instead of just looking at them bit by bit.

For example:

entity Comparator is port(a,b in: std_logic_vector (2 downto 0); out1, out2 out: std_logic); end Comparator; architecture behavioural of Comparator1 is begin if a = b then out1 <= '1' else if /= then out2 <= '1' end if; end behaviour;

Is this possible?


The answer is yes, you can compare two array types of the same type and subtype indication directly.

However your example code isn't valid.

The result of the expression a=b is boolean. You convert that to std_logic by assigning out1 and out2. An if statement in this context has to be in a process statement. Also you don't need two outputs:

architecture foo of Comparator1 is begin UNLABELED: process (a,b) begin if a = b then out1 <= '1'; else out1 <= '0'; end if; end process; end architecture;

Alternative a concurrent signal assignment statement, a conditional signal assignment that has an equivalent process to that above:

architecture fum of Comparator1 is begin UNLABELED: out1 <= '1' when a = b else '0'; end architecture;


You can also use to_integer(unsigned(a)) and threat them as integers. For example:

IF(to_integer(unsigned(a)) < to_integer(unsigned(b))) THEN


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